Performance-based optical proximity correction methodology

Authors:
Siew-Hong Teh;Chun-Huat Heng;Arthur Tay
Affiliations:
Department of Electrical and Computer Engineering, National University of Singapore, Singapore;Department of Electrical and Computer Engineering, National University of Singapore, Singapore;Department of Electrical and Computer Engineering, National University of Singapore, Singapore
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

Citing 12
Cited 0

A cost-driven lithographic correction methodology based on off-the-shelf sizing tools

Proceedings of the 40th annual Design Automation Conference
Fast optical and process proximity correction algorithms for integrated circuit manufacturing

Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Standard cell characterization considering lithography induced variations

Proceedings of the 43rd annual Design Automation Conference
A unified non-rectangular device and circuit simulation model for timing and power

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation

Proceedings of the 44th annual Design Automation Conference
Design-process integration for performance-based OPC framework

Proceedings of the 45th annual Design Automation Conference
Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes

Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes
Electrically driven optical proximity correction based on linear programming

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Cost of ownership - projecting the future

Microelectronic Engineering
Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mask Design for Optical Microlithography—An Inverse Imaging Problem

IEEE Transactions on Image Processing

Quantified Score

Hi-index	0.03

Visualization

Abstract

The rapid reduction in critical dimension of integrated circuits has lead to substantial mask data expansion for mask design based on traditional model-based full-chip optical proximity correction (OPC). Conventional EPE-OPC is mainly based on edge placement error (EPE) without consideration of its effect on circuit performance; often resulting in an overcorrected OPC mask with little improvement in circuit performance at the expense of much higher cost. In this paper, a performance-based OPC (PB-OPC) methodology is proposed taking into account both performance and cost. A less complex mask is generated based on the performance matching criteria. The framework exploits the in situ estimated postlithography performance deviation error to drive the customized mask design algorithm. In particular, device PB-OPC (DPB-OPC) was deployed to systematically synthesize both polysilicon and diffusion masks by using mean drive current deviation as the controlled performance index. The proposed approach is validated via detailed simulation using 65-nm foundry libraries and IEEE International Symposium on Circuits and Systems 1985 (ISCAS'85) benchmark circuits. When compared to conventional performance-aware EPE-OPC approach, the proposed DPB-OPC achieved 34% average reduction in mask size and up to 13.5% reduction in mean drive current deviation within reasonable run time.