Performance Driven OPC for Mask Cost Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Advanced timing analysis based on post-OPC extraction of critical dimensions
Proceedings of the 42nd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
Performance-based optical proximity correction methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for propagating design tolerances to shape tolerances for use in manufacturing
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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Conventional optical proximity correction (OPC) tools aim to minimize edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve. In addition, prohibitively high mask complexity is incurred, leading to high mask cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with accurate electrical modeling of resist contours to predict the on/off current through a transistor gate. The computation of mask edge movements is cast as a linear program based on optical and electrical sensitivities. The objective is to minimize the error in saturation current between printed and target shapes. This optimization is then solved with fast runtime. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC. This is achieved at less than 26% runtime overheads, while also lowering mask complexity by up to 43%. The results confirm that better timing accuracy can be achieved despite larger edge placement error.