Metal filling impact on standard cells: definition of the metal fill corner concept
Proceedings of the 21st annual symposium on Integrated circuits and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Metal fills, which are used to reduce metal thickness variations due to chemical-mechanical polishing (CMP), increase the capacitances in a circuit. Although current extraction tools are accurate in handling grounded fills and regular interconnects, for floating fills, these tools are based on certain approximations, such as assuming that floating fills are grounded or each fill is merged with neighboring ones. To reduce such inaccuracies, we provide a design of experiments (DOE), which will be used in addition to what is available in the extraction tools for regular interconnects. Through the proposed DOE set, a design or mask house can generate normalized fill tables to remove the inaccuracies of the extraction tools in the presence of floating fills. The capacitance values are updated using these normalized fill tables. The proposed DOE enables extensive analyses of the fill impacts on coupling capacitances. We show through extensive 3D field solver simulations that the assumptions used in extractors result in significant inaccuracies. We present analyses of fill impacts for an example technology, and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms.