Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Package level interconnect options
Proceedings of the 2005 international workshop on System level interconnect prediction
| Hi-index | 2.88 |
Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400^oC range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. TSV aspect ratios can vary as function of the integration scheme, for instance in a via-last or via-middle flow, and thus barrier continuity requires conformality which guarantees the presence of a diffusion barrier until the bottom of the TSV. Target conformality can either be obtained by PVD, typically for TSV A.R.=