A fast and accurate technique to optimize characterization tables for logic synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Timing
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Making fast buffer insertion even faster via approximation techniques
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
A current source model for CMOS logic cells considering multiple input switching and stack effect
Proceedings of the conference on Design, automation and test in Europe
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Foundations and Trends in Electronic Design Automation
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Fundamentals of Modern VLSI Devices
Fundamentals of Modern VLSI Devices
Body bias voltage computations for process and temperature compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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State-of-the-art timing tools are built around the use of current source models (CSMs), which have proven to be fast and accurate in enabling the analysis of large circuits. As circuits become increasingly exposed to process and temperature variations, there is a strong need to augment these models to account for thermal effects and for the impact of adaptive body biasing, a compensatory technique that is used to overcome on-chip variations. However, a straightforward extension of CSMs to incorporate timing analysis at multiple body biases and temperatures results in unreasonably large characterization tables for each cell. We propose a new approach to compactly capture body bias and temperature effects within a mainstream CSM framework. Our approach features a table reduction method for compaction of tables and a fast and novel waveform sensitivity method for timing evaluation under any body bias and temperature condition. On a 45-nm technology, we demonstrate high accuracy, with mean errors of under 4%in both slew and delay as compared to HSPICE. We show a speedup of over five orders of magnitude over HSPICE and a speedup of about 92× over conventional CSMs.