A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A false-path aware formal static timing analyzer considering simultaneous input transitions
Proceedings of the 46th Annual Design Automation Conference
Current source modeling in the presence of body bias
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a current source model (CSM) of a CMOS logic cell, which captures simultaneous switching of multiple inputs while accounting for the effect of internal node voltages of the logic cell. Characterization procedures for various components of the proposed CSM are described and application of the model to output waveform computation is discussed. Experimental results to assess the accuracy and efficiency of the proposed multiple input switching CSM in the context of noise and timing analyses in VLSI circuits are reported.