Skew-tolerant circuit design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Timing
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast and Accurate Waveform Analysis with Current Source Models
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A current source model (CSM) for CMOS logic cells is presented, which can be used for accurate noise and delay analysis in CMOS VLSI circuits. CS modeling is broadly considered as the method of choice for modern static timing and noise analysis tools. Unfortunately, the existing CSMs are only applicable to combinational logic cells. In addition to multistage logic nature of the sequential cells, the main difficulty in developing a CSM for these cells is the presence of feedback loops. This paper begins by presenting a highly accurate CSM for combinational logic cells, followed by models for common sequential cells, including latches and master slave flip-flops. The proposed model addresses these problems by characterizing the cell with suitable nonlinear CSs and capacitive components. Given the input and clock voltage waveforms of arbitrary shapes, our new model can accurately compute the output voltage waveform of the sequential cell. Experimental results demonstrate close-to-SPICE waveforms with three orders of magnitude speedup.