Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Driver waveform computation for timing analysis with multiple voltage threshold driver models
Proceedings of the 45th annual Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
An Efficient Method for Fast Delay and SI Calculation Using Current Source Models
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SWAT: simulator for waveform-accurate timing including parameter variations and transistor aging
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a novel method for generating current source models (CSMs) for logic cells that efficiently captures the influences of parameter variation and supply voltage drops. The characterization exploits topological information from the transistor netlist resulting in typically 80x faster CSM library generation. The parametric CSMs have been integrated into a commercial FastSPICE simulator to further accelerate path-based timing analysis with transistor level accuracy. Without loss of accuracy, simulation times were reduced by 4x to 98x.