A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Towards a more physical approach to gate modeling for timing, noise, and power
Proceedings of the 45th annual Design Automation Conference
A moment-based effective characterization waveform for static timing analysis
Proceedings of the 46th Annual Design Automation Conference
Efficient compression and handling of current source model library waveforms
Proceedings of the Conference on Design, Automation and Test in Europe
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs formalize a class of gate models which include the existing industry standards, such as CCS and ECSM driver models as special cases. The analysis technique relies on primary MVTM characterization data and does not require explicit instantiation of controlled current source models. Therefore, the method is more accurate, efficient, and general than traditional transient analysis. The theoretical results are validated by detailed simulations and use within full chip timing analysis.