Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Calculating the effective capacitance for the RC interconnect in VDSM technologies
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Driver waveform computation for timing analysis with multiple voltage threshold driver models
Proceedings of the 45th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
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Timing, noise, and power analysis have historically relied on high level, black-box, non-physical logic library models. Moreover, these models were of a look-up type, i.e. precharacterized for practically all the possible environments in which they would be eventually used. The evolution of the VLSI technology towards nanometer sized features made this characterization methodology impractical. Increasingly, the space of all possible environments grew too rich to be fully covered during characterization. In the past decade, the so-called effective capacitance was introduced to provide some analysis capability to gate models, i.e., the ability to evaluate in the presence of RC loads, although characterized with capacitive loads only. In current and future VLSI technologies, such simple extensions no longer provide the required accuracy. Increasingly, models of logic gates must retain elements of the electrical behavior of the circuit in order to provide accurate timing, noise, and power information. This poses a new challenge on the analysis algorithms, now required to handle an enhanced level of detail in modeling without significantly degrading the overall efficiency of the application.