A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Noise characterization of static CMOS gates
Proceedings of the 41st annual Design Automation Conference
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards a more physical approach to gate modeling for timing, noise, and power
Proceedings of the 45th annual Design Automation Conference
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We present a noise-driven effective capacitance method for estimating the combined propagation noise and crosstalk noise. Gate propagation noise rules are efficiently calculated inside the Ceff procedure to determine a linear Thevenin model of the victim driver. A voltage-dependent current source model [2, 6] of the driver, along with a load capacitor is analyzed to generate the gate output waveform, from which noise rules are directly extracted. This method removes potential errors introduced in traditional look-up table or fitted-equation based noise rules. The linear driver Thevenin model can then be employed to analyze the propagation noise, while the same Thevenin resistance can be used to analyze the crosstalk noise. The combined coupling and propagation noise can then be estimated using superposition. In this work, we extend the popular timing-driven effective capacitance method into the noise domain. Similar to the effective capacitance method in timing analysis, this technique can successfully separate the nonlinear driver analysis from the linear interconnect analysis. In addition, the linear driver model can significantly ease the task of finding the worst-case peak alignment among all the victim and aggressor noise sources. Experimental results on both RC and RLC nets from industry designs show both accuracy and efficiency compared to SPICE results.