ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Automated timing model generation
Proceedings of the 39th annual Design Automation Conference
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Temporofunctional crosstalk noise analysis
Proceedings of the 40th annual Design Automation Conference
Static noise analysis with noise windows
Proceedings of the 40th annual Design Automation Conference
Noise characterization of static CMOS gates
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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A voltage and current-accurate boundary model is presented for custom and hard macro blocks. For a given hierarchical transistor-level netlist of a digital macro block we identify a small but sufficient subset of transistors that form a boundary netlist for performing fast noise analysis. The model contains layers of the original transistors and parasitics around the block boundary. Therefore it can be used with any noise analysis method, including accurate SPICE simulation. We present definition of the Transistor Boundary Noise Model (TBNM) for several types of circuits, the algorithm to extract it efficiently, and how to sensitize the new netlist for on-the-fly simulation or library precharacterization. The use of TBNM enabled automated noise analysis of designs that include many large custom blocks and embedded memory by speeding up their noise characterization by 2 to 3 orders of magnitude.