The design and implementation of PowerMill
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
SOI circuit design concepts
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast statistical circuit analysis with finite-point based transistor model
Proceedings of the conference on Design, automation and test in Europe
MOSFET modeling for 45nm and beyond
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
Finite-point-based transistor model: a new approach to fast circuit simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Progress in semiconductor process technology has made SOItransistors one of the most promising candidates for high performanceand low power designs. With smaller diffusion capacitances,SOI transistors switch significantly faster than theirtraditional bulk MOS counterparts and consume less power perswitching. However, design and simulation of SOI MOS circuits ismore challenging due to more complex behavior of an SOI transistorinvolving floating body effects, delay dependence on history oftransistor switching, bipolar effect and others. This paper isdevoted to developing a fast table model of SOI transistors, suitablefor use in fast transistor level simulators. We propose usingbody charge instead of body potential as an independent variableof the model to improve convergence of circuit simulation integrationalgorithm. SOI transistor has one additional terminal comparedwith the bulk MOSFET and hence requires larger tables tomodel. We propose a novel transformation to reduce number oftable dimensions and as a result to make the size of the tables reasonable.The paper also presents efficient implementation of ourSOI transistor table model using piece-wise polynomial approximation,nonuniform grid discretization, and splitting the transistormodel into the model of its equilibrium and non equilibrium states.The effectiveness of the proposed model is demonstrated byemploying it in a fast transistor level simulator to simulate highperformance industrial SOI microprocessor circuits.