Timing Arc Based Logic Analysis for false noise reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
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We study the problem of identifying the complete set ofpairs of input patterns that can cause different types of hazardsto appear at a circuit line. A novel methodology toimplicitly identify all possible input configurations is proposed.The technique is based on a systematic derivationof the conditions for the occurrence of static and dynamichazards at a line, which are subsequently formulated asBoolean functions defined over variables representing theprimary input signals. Our experimental results demonstratethat the proposed approach is very promising andoutperforms existing approaches. In addition, they showthat a proposed solution for the decision problem of hazardexistence at a circuit line is very efficient.