Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Constrained aggressor set selection for maximum coupling noise
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Feasible aggressor-set identification under constraints for maximum coupling noise
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing Arc Based Logic Analysis for false noise reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As integrated circuit technology continues to scale into the nanometer regime, the effect of crosstalk on circuit timing becomes significant. Static timing analysis shows that crosstalk routinely adds 10% to 20% delay to the critical path of a design. However, many aggressor/victim switching combinations are infeasible due to inherent circuit operating constraints, thereby contributing to the mismatch between timing analysis and actual silicon performance. This paper proposes a novel timing analysis technique where circuit functionality, delay, and crosstalk are simultaneously considered using time-sliced Boolean logic. The worst case timing on the critical path end point is calculated to be the minimum and maximum time slices where the timed Boolean logic on its coupled fanin cone is satisfiable. Up to 1-ns reduction in timing pessimism on 0.13-μm industrial designs was observed. Furthermore, results on special circuit topologies such as data busses with coupled interleaved inverters match well with results from exhaustive Spice simulation sweeps with up to 50% reduction in timing pessimism over timing analysis that does not consider false coupling.