Timing Arc Based Logic Analysis for false noise reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
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Noise affects circuit operation by varying circuit delays and causing latches to capture incorrect values. Conventional noise analysis techniques can detect some of such noise faults, but accurate analysis requires a careful examination of timing and functional properties of the circuit. In this paper, a method of characterizing correlation of signal transitions in nets by considering in a unified way both timing and functionality of the signals is proposed. An analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered is described. The timed-Boolean logic is used to characterize signal transitions in a time interval, and correlations are checked by solving Boolean satisfiability (SAT) between aggressor and victim transitions under the min-max delay model for gates. The method is applicable for checking noise faults at a single net, on a path, or in a cone of logic. The proposed technique is scalable as it keeps the size of Boolean formulation linear to the size of the modeled circuit. It has been applied on a set of large circuits, eliminating up to 50% of noise delay faults reported by a conventional noise-analysis method.