Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis

Authors:
Bipul C. Paul;Kaushik Roy
Affiliations:
-;-
Venue:
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Year:
2002

Citing 0
Cited 4

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Journal of Electronic Testing: Theory and Applications
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults

Proceedings of the conference on Design, automation and test in Europe
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits

Proceedings of the 19th ACM Great Lakes symposium on VLSI
On ATPG for multiple aggressor crosstalk faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

In deep submicron (DSM) circuits the critical path obtained from static timing analysis may often be incorrect due to significant effect of cross-talk. In this paper we present a new algorithm based on timed automatic test pattern generation (ATPG) to generate a list of critical paths of a circuit and the corresponding input vectors to sensitize these paths under cross-talk. The algorithm based on modified PODEM handles multiple aggressors to a victim node and properly activates the aggressors to obtain maximum coupling to the victim. Several circuits were tested using this algorithm and results were verified by HSPICE simulation.