ATPG for Noise-Induced Switch Failures in Domino Logic
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated with in the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved w thout significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.