Logic synthesis
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Estimation for maximum instantaneous current through supply lines for CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
ATPG for Noise-Induced Switch Failures in Domino Logic
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified framework for generating all propagation functions for logic errors and events
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional timing analysis using ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
Functional timing analysis made fast and general
Proceedings of the 49th Annual Design Automation Conference
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
Automatic test pattern generation for delay defects using timed characteristic functions
Proceedings of the International Conference on Computer-Aided Design
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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Timing analysis is critical for many circuit optimizations. An accurate timing analysis can be achieved by finding input vectors that simultaneously satisfy both functional and temporal requirements. The problem of finding such input vectors can be modeled as a Boolean equation called the timed characteristic function (TCF). Despite the usefulness of the TCF, traditional TCF construction and solving is slow for large circuits. In this paper, we present a more efficient way to use the TCF. On average, our method is much faster than other most recent works.