Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Concurrent Delay Testing in Totally Self-Checking Systems
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
A Totally Self-Checking 1-out-of-3 Code Error Indicator
Journal of Electronic Testing: Theory and Applications
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
Formal Methods in System Design
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
General framework for removal of clock network pessimism
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Totally Self-checking 1-out-of-3 Code Error Indicator
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WCRT algebra and interfaces for Esterel-style synchronous processing
Proceedings of the Conference on Design, Automation and Test in Europe
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
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