Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults
Journal of Electronic Testing: Theory and Applications
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Totally Self-Checking 1-out-of-3 Code Error Indicator
Journal of Electronic Testing: Theory and Applications
TIMBER: time borrowing and error relaying for online timing error resilience
Proceedings of the Conference on Design, Automation and Test in Europe
Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance andhigh density VLSI circuits have to be satisfied in critical applications. This can be achieved by using concurrent delay testing.In this paper a novel idea for concurrent detection of two-rail path delay faults is introduced. It is shown that TSC two-rail code error indicators that monitor pairs of paths with similar propagation delays can be used for concurrent delay testing. Our technique is applied to TSC two-rail code checkers as well as to duplication systems which are the most widely used TSC systems. The design of TSC two-rail code checkers and TSC duplication systems with respect to two-rail path delay faults is achieved for first time in the open literature.