On the Design of Combinational Totally Self-Checking 1-out-of-3 Code Checkers
IEEE Transactions on Computers
An Efficient TSC 1-out-of-3 Code Checker
IEEE Transactions on Computers
Self-checking CMOS circuits using pass-transistor logic
Journal of Electronic Testing: Theory and Applications
Concurrent Delay Testing in Totally Self-Checking Systems
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
A Highly Testable 1-out-of-3 CMOS Checker
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
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In this paper, an asynchronous TSC 1-out-of-3 (1/3) codeerror indicator is introduced that memorizes erroneous 1/3 codeinputs 000, 011, 101, 110, 111 with time duration greater than adiscrimination time T. Such an error indicator is used todiscriminate transient erroneous 1/3 code inputs from real ones aswell as to detect faults that cause logical errors and delay faults(short or long) altering the circuit delay outside its specifiedlimits (upper or lower bounds) without causing logical errors. To ourknowledge, this error indicator is the first TSC 1/3 code errorindicator proposed in the open literature.