A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Switching activity estimation using limited depth reconvergent path analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transition density: a new measure of activity in digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
A new probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a new probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe the temporal and spatial correlation in terms of the associated zero delay-based parameters, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. Comparative study and analysis of benchmark circuits demonstrates the accuracy of the proposed method.