Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Logic emulation with virtual wires
Readings in hardware/software co-design
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Architectural Design of a Three Dimensional FPGA
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cluster based dynamic area-array I/O planning for flip chip technology
Microelectronic Engineering
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Area-IO provide a way to eliminate the IO bottleneck of field programmable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and the propensity of logic to demand it. Whether the incorporation of area IO into FPLD architectures has undesirable side effects is a question that has not yet been answered. In this paper, we examine the architectural impact of area-IO on FPLDs from a theoretical and experimental standpoint and show that the introduction of area IO generally improves the routability and delay of a set of benchmark circuits.