Introduction to algorithms
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
FPGA-based emulator architectures
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Design of FPGAs with area I/O for field programmable MCM
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-FPGA systems
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
IEEE Transactions on Parallel and Distributed Systems
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Routability improvement using dynamic interconnect architecture
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
VIRTUAL WIRES: OVERCOMING PIN LIMITATIONS IN FPGA-BASED LOGIC EMULATION
VIRTUAL WIRES: OVERCOMING PIN LIMITATIONS IN FPGA-BASED LOGIC EMULATION
Novel techniques for high performance field-programmable logic devices
Novel techniques for high performance field-programmable logic devices
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Logic emulation enables designers to functionally verify complex integrated circuits prior to chip fabrication. However, traditional FPGA-based logic emulators have poor interchip communication bandwidth, commonly limiting gate utilization to less than 20%. Global routing contention mandates the use of expensive crossbar and PC-board technology in a system of otherwise low-cost commodity parts. Even with crossbar technology, current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires, and pipelining these connections at the maximum clocking frequency of the FPGA. The resulting increase in bandwidth allows effective use of low-dimension direct interconnect. The size of the FPGA array can be decreased as well, resulting in low-cost logic emulation. This paper covers major contributions of the MIT Virtual Wires project. In the context of a complete emulation system, we analyze phase-based static scheduling and routing algorithms, present virtual wires synthesis methodologies, and overview an operational prototype with 20K-gate boards. Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45%. Theoretical analysis predicts that virtual wires emulation scales with FPGA size and average routing distance, while traditional emulation does not.