Logic emulation with virtual wires
Readings in hardware/software co-design
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Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneously and are only switched at emulation clocking speeds. Virtual Wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency of the FPGA. A virtual wire connects a logical output of one FPGA to a logical input on another FPGA. Virtual Wires relax the absolute limits imposed on gate utilization. The resulting increase in bandwidth reduces the need for global interconnect, allowing effective use of low dimension inter-chip connections. This thesis presents and analyzes the concept of Virtual Wires, and describes a Virtual Wires compiler which utilizes static routing and relies on minimal hardware support. Results from compiling netlists for the 18K gate Sparcle microprocessor and the 86K gate Alewife Communications and Memory Management Unit indicate that Virtual Wires can increase FPGA gate utilization beyond 80 percent without a significant slowdown in emulation speed. Thesis Supervisor: Anant Agarwal Title: Associate Professor of Computer Science and Electrical Engineering