Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Technologies and Utilization fo Field Programmable Gate Arrays
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
ORCA: A New Architecture for High-Performance FPLs
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
Logic emulation with virtual wires
Readings in hardware/software co-design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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Abstract: Field programmable gate arrays (FPGAs) have formed the basis for high performance and affordable computing systems. FPGA based logic simulators can emulate complex logic designs at clock speeds of several orders of magnitude faster than even accelerated software simulators, while FPGA based prototyping systems provide great flexibility in rapid prototyping and system verification. However, besides FPGA pin limitation, existing FPGA based systems also meet the problem of improving the routability of interconnect networks in the architecture design. We present a dynamic architecture for FPGA based computing systems with field programmable gate arrays and dynamic field programmable interconnect devices. Our architecture has advantages on FPGA gate utilization as well as on routability of interconnect networks. The central principle of this new architecture as based on the concept of efficiently exploiting the potential communication bandwidth of interconnect resources. By dynamically reconfiguring the interconnect networks, FPGA pins and interconnect resources are efficiently reused. In this way, this new architecture not only overcomes FPGA pin limitations, but also greatly increases the routability of interconnect networks, resulting in higher overall performance of FPGA based systems.