A quantitative approach to functional debugging
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Enhanced visibility and performance in functional verification by reconstruction
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cut-based functional debugging for programmable systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic emulation with virtual wires
Readings in hardware/software co-design
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Si-Emulation: System Verification Using Simulation and Emulation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA
ATS '04 Proceedings of the 13th Asian Test Symposium
Hybrid Approach to Faster Functional Verification with Full Visibility
IEEE Design & Test
Using triggers for emulation of opportunistic networking
MobiOpp '10 Proceedings of the Second International Workshop on Mobile Opportunistic Networking
Improving the observability and controllability of datapaths for emulation-based debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable hybrid verification system based on HDL slicing
HLDVT '11 Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop
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Hybrid functional verification and debug systems which combine high execution speed of logic emulators and full observability and controllability of software simulators are widely used, but suffer from scalability problem since software simulators cannot handle large and complex System-on-chip (SoC) designs efficiently, restricting their application to only relatively small designs. This paper presents a completely scalable hybrid verification and debug system based on dynamically reconfigurable co-simulation. Unlike existing systems, it allows one or more component logic blocks of a SoC to run on simulator for debugging while rest of the design still runs on emulator. The full design under test (DUT) is run on emulator at near hardware speed for long test sequences, and on error detection one or more logic blocks are transparently switched over to simulation for debugging, initializing the system as a piecewise co-simulator. Logic blocks can be flexibly relocated between simulator and emulator dynamically, without going through time consuming design recompilation phase, allowing designers to quickly debug functional issues. Application of the system to verification of real complex designs shows the effectiveness of our approach.