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ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
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Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
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MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
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ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Asim: A Performance Model Framework
Computer
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IEEE Micro
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
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Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
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COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
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Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
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ACM Transactions on Architecture and Code Optimization (TACO)
An analysis of a resource efficient checkpoint architecture
ACM Transactions on Architecture and Code Optimization (TACO)
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HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
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IBM Journal of Research and Development
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ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
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Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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ACM Transactions on Architecture and Code Optimization (TACO)
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This paper presents a novel high performance substrate for building energy-efficient out-of-order superscalar cores. The architecture does not require a reorder buffer or physical registers for register renaming and instruction retirement. Instead, it uses a large number of virtual register IDs for register renaming, a physical register file of the same size as the logical register file, and checkpoints to bulk retire instructions and to recover from exceptions and branch mispredictions. By eliminating physical register renaming and the reorder buffer, the architecture not only eliminates complex power hungry hardware structures, but also reduces reorder buffer capacity stalls when execution encounters long delays from data cache misses, thus improving performance. The paper presents performance and power evaluation of this new architecture using Spec 2006 benchmarks. The performance data was collected using an x86 ASIM-based performance simulator from Intel Labs. The data shows that the new architecture improves performance of a 2-wide out-of-order x86 processor core by an average of 4.2%, while saving 43% of the energy consumption of the reorder buffer and retirement register file functional block.