Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers

Authors:
Haitham Akkary;Ravi Rajwar;Srikanth T. Srinivasan
Affiliations:
Portland State University;Intel Microarchitecture Research Lab;Intel Microarchitecture Research Lab
Venue:
IEEE Micro
Year:
2003

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Abstract

Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an efficient means of increasing the instruction window size without requiring large, cycle-critical structures, and provides a promising microarchitecture for future high-performance processors.