Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Limits of control flow on parallelism
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Dynamically scheduled VLIW processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Tuning the Pentium Pro Microarchitecture
IEEE Micro
Developing the AMD-K5 Architecture
IEEE Micro
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
Advanced performance features of the 64-bit PA-8000
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Microarchitecture of HaL's CPU
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Internal architecture of Alpha 21164 microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Instruction Level Parallel Processors---A New Architectural Model for Simulation and Analysis
Instruction Level Parallel Processors---A New Architectural Model for Simulation and Analysis
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Discerning the dominant out-of-order performance advantage: is it speculation or dynamism?
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
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Recently, high performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These designs are complex and have frequently shown disappointing performance. A complementary approach is the use of static scheduling techniques to exploit the same parallelism. We describe some of the tradeoffs between the use of static and dynamic scheduling techniques and show that with appropriate scheduling, low complexity designs using only static scheduling have significant advantages over high complexity designs using dynamic scheduling in real systems.