Internal architecture of Alpha 21164 microprocessor

Authors:
P. Bannon;J. Keller
Affiliations:
-;-
Venue:
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Year:
1995

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Abstract

The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.