Microarchitecture of HaL's CPU

Authors:
N. Patkar;A. Katsuno;S. Li;T. Maruyama;S. Savkar;M. Simone;G. Shen;R. Swami;D. Tovey
Affiliations:
-;-;-;-;-;-;-;-;-
Venue:
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Year:
1995

Citing 0
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Abstract

The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.