Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor

Authors:
M. Simone;A. Essen;A. Ike;A. Krishnamoorthy;T. Maruyama;N. Patkar;M. Ramaswami;M. Shebanow;V. Thirumalaiswamy;D. Tovey
Affiliations:
HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA;HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA;Fujitsu Limited, Kawasaki, Japan;HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA;Fujitsu Limited, Kawasaki, Japan;HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA;HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA;Cyrix Corp., Richardson, Texas;HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA;HaL Computer Systems, Inc., 1315 Dell Avenue, Campbell, CA
Venue:
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Year:
1995

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Abstract

The implementation of a superscalar, speculative execution SPARC-V9 microprocessor incorporating Restricted Data Flow principles required many design trade-offs. Consideration was given to both performance and cost. Performance is largely a function of cycle time and instructions executed per cycle while cost is primarily a function of die area. Here we describe our Restricted Data Flow implementation and the means with which we arrived at its configuration. Future semiconductor technology advances will allow these trade-offs to be relaxed and higher performance Restricted Data Flow machines to be built.