Simple Bounds on Serial Signature Analysis Aliasing for Random Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
LegoSim: simulation of embedded kernels over Pthreads
Journal on Educational Resources in Computing (JERIC)
Design Verification of a Super-Scalar RISC Processor
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
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This paper describes several implementation techniques used in HAL's 500 KIPS SPARC V9 behavioral model. Beyond presenting the details of our processor model, we describe several areas of innovation: architectural state-vector capture for injection into a gate-level hardware model, using an EDC polynomial-based signature scheme to verify a hardware design; obtaining accurate kernel and user-mode instruction trace data.