A Case for Direct-Mapped Caches
Computer
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A comparison of dynamic branch predictors that use two levels of branch history
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Next cache line and set prediction
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Correlation and aliasing in dynamic branch predictors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
UltraSPARC: the next generation superscalar 64-bit SPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Microarchitecture of HaL's CPU
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Design of the UltraSPARC Instruction Fetch Unit
Design of the UltraSPARC Instruction Fetch Unit
Speeding Up Target Address Generation Using a Self-indexed FTB (Research Note)
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
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Designing a modern microprocessor is a complex task that demands careful balance between cycle time, cycle-per-instruction and area costs. In particular, the instruction fetch unit greatly affects the performance of a multi-issue processor. It must provide adequate bandwidth to sustain peak instruction issue rate and must predict future instruction sequences with high accuracy. In the UltraSPARC prefetch and dispatch unit design, we examined a technique that combined two prediction methods: predictive set-associative cache and in-cache prediction. This combination was compared with alternative designs such as direct-mapped and set-associative caches, and a branch history table and a branch target buffer. We chose the combined prediction technique for its fast cycle time, lower cycle-per-instruction, and lower area costs. This paper summarizes the trade-off decisions made in the design of the UltraSPARC instruction prefetch and dispatch unit.