A comprehensive instruction fetch mechanism for a processor supporting speculative execution
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Next cache line and set prediction
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Design decisions influencing the UltraSPARC's instruction fetch architecture
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
A scalable front-end architecture for fast instruction delivery
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
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The fetch target buffer (FTB) holds information on basic blocks to predict taken branches in the fetch stream and also their target addresses. We propose a variation to FTB, the self-indexed FTB, which, through an extra level of indirection, provides the high hit rate of a relatively large, high-associative FTB with the fast access delay of a small, direct-mapped FTB. The critical and most frequent operation -predicting the next FTB entry- is speeded up, whilst less frequent operations -such as recovering from FTB misses- are slightly slowed down. The new design is both analyzed and simulated. Performance increase on a 512-entry FTB is estimated at between 15% and 30%.