SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Alpha implementations and architecture: complete reference and guide
Alpha implementations and architecture: complete reference and guide
Programming parallel algorithms
Communications of the ACM
A practitioner's guide to RISC microprocessor architecture
A practitioner's guide to RISC microprocessor architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The PowerPC 604 RISC microprocessor
IEEE Micro
VIS Speeds New Media Processing
IEEE Micro
Subword Parallelism with MAX-2
IEEE Micro
RIPEMD-160: A Strengthened Version of RIPEMD
Proceedings of the Third International Workshop on Fast Software Encryption
Proceedings of the Third International Workshop on Fast Software Encryption
MMH: Software Message Authentication in the Gbit/Second Rates
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
HAS-V: A New Hash Function with Variable Output Length
SAC '00 Proceedings of the 7th Annual International Workshop on Selected Areas in Cryptography
Performance Analysis and Parallel Implementation of Dedicated Hash Functions
EUROCRYPT '02 Proceedings of the International Conference on the Theory and Applications of Cryptographic Techniques: Advances in Cryptology
Recent Developments in the Design of Conventional Cryptographic Algorithms
State of the Art in Applied Cryptography, Course on Computer Security and Industrial Cryptography - Revised Lectures
Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs
Computers and Electrical Engineering
On the hardware implementation of RIPEMD processor: Networking high speed hashing, up to 2Gbps
Computers and Electrical Engineering
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To enhance system performance computer architectures tend to incorporate an increasing number of parallel execution units. This paper shows that the new generation of MD4-based customized hash functions (RIPEMD-128, RIPEMD-160, SHA-1) contains much more software parallelism than any of these computer architectures is currently able to provide. It is conjectured that the parallelism found in SHA-1 is a design principle. The critical path of SHA-1 is twice as short as that of its closest contender RIPEMD-160, but realizing it would require a 7-way multiple-issue architecture. It will also be shown that, due to the organization of RIPEMD-160 in two independent lines, it will probably be easier for future architectures to exploit its software parallelism.