Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
The PowerPC performance modeling methodology
Communications of the ACM
The PowerPC architecture: a specification for a new family of RISC processors
The PowerPC architecture: a specification for a new family of RISC processors
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital Technical Journal - Special 10th anniversary issue
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance evaluation of the PowerPC 620 microarchitecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Bounds modelling and compiler optimizations for superscalar performance tuning
Journal of Systems Architecture: the EUROMICRO Journal - Special double issue on microprocessor architecture
RuleBase: Model Checking at IBM
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
3.3 Performance Test Case Generation for Microprocessors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
IBM Journal of Research and Development
Phaser: phased methodology for modeling the system-level effects of soft errors
IBM Journal of Research and Development
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 0.00 |
Microprocessor design teams use a combination ofsimulation-based and formal verification techniques tovalidate the pre-silicon models prior to “tape-out” and chipfabrication. Pseudo-random test case generation to “cover”the architectural space is still relied upon as theprincipal means to identify design bugs. However, suchmethods are limited to functional bugs only. Detection anddiagnosis of timing (performance) bugs at the architecturallevel is largely an expert job. Architects guide theperformance team to run manually generated test cases tovalidate the design from a performance viewpoint. In thispaper, we will review some of the new approaches being triedout to automate the generation of performance test cases. Wewill show how this can be done within the basic framework ofcurrent functional validation and testing of pre-siliconprocessor models. Three categories of “reference”specifications are used in determining the defect-freepipeline timing behavior associated with generated testcases: (a) axiomatic specifications of intrinsic machinelatencies and bandwidths; (b) proven analytical models forsimple basic block and loop test cases; and, (c) a stablereference behavioral/functional (pre-RTL) model of theprocessor under development. We report experimental resultsobtained in performance validation studies applied to realPowerPC™ processor development projects.