The PowerPC architecture: a specification for a new family of RISC processors
The PowerPC architecture: a specification for a new family of RISC processors
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Performance evaluation and validation of microprocessors
SIGMETRICS '99 Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A full lifecycle performance verification methodology for multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such test cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre-and post-silicon stages of development.