Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Instruction cache fetch policies for speculative execution
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
The Effect of Speculative Execution on Cache Performance
Proceedings of the 8th International Symposium on Parallel Processing
3.3 Performance Test Case Generation for Microprocessors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Mispredicted Path Cache Effects
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies
Proceedings of the 31st annual international symposium on Computer architecture
Automatic Synthesis of High-Speed Processor Simulators
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A superscalar simulation employing poisson distributed stalls
Computers and Electrical Engineering
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This paper presents a new PowerPC-based performance simulation tool that has full-function capability. The new tool fMW is developed from the integration of the functional simulator PSIM and the cycle-accurate performance simulator MW. The two tools work in a tightly coupled fashion to facilitate new simulation capabilities. fMW is capable of: 1) simulating mispredicted path instructions and value prediction techniques; 2) simulating multiple instruction streams of a program; and 3) verifying test sequences for the validation of speculation and recovery mechanisms. The fMW tool is implemented and used in two recent studies. The first study examines the effects mispredicted path instructions have on the instruction cache hierarchy. The second study quantifies the coverage achieved by test sequences for the thorough validation of register renaming and out-of-order execution mechanisms. These studies demonstrate the weaknesses and inaccuracies of previous tools, while illustrating the strengths of the new fMW tool.