Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
IEEE Transactions on Computers
ATOM: a system for building customized program analysis tools
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Mint Tutorial and User Manual
Speculative Memory Cloaking and Bypassing
International Journal of Parallel Programming - Special issue on the 30th annual ACM/IEEE international symposium on microarchitecture, part II
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Measuring experimental error in microprocessor simulation
SSR '01 Proceedings of the 2001 symposium on Software reusability: putting software reuse in context
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction
IEEE Transactions on Computers
Using the Alfa-1 simulated processor for educational purposes
Journal on Educational Resources in Computing (JERIC)
Measuring Experimental Error in Microprocessor Simulation
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Designing an Alpha Microprocessor
Computer
Asim: A Performance Model Framework
Computer
Experiences in modeling and simulation of computer architectures in DEVS
Transactions of the Society for Computer Simulation International - Recent advances in DEVS methodology--part II
Parallel simulation of chip-multiprocessor architectures
ACM Transactions on Modeling and Computer Simulation (TOMACS)
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Philosophical foundations of computer simulation validation
Simulation and Gaming
Performance modeling for early analysis of multi-core systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A performance methodology for commercial servers
IBM Journal of Research and Development
Hi-index | 4.11 |
If there ever was a time when the architecture of a high-performance micro-processor could spring completely formed from the mind of a single engineer, that time has passed. Modern microprocessor architectures are the result of invention and progressive refinement by a team. Producing a finished microprocessor takes the effort of many engineers in many disciplines, but the first step requires that an architecture team sketch out the organization of a chip. The teams that designed Digital's Alpha processors are guided in large part by an executable performance model. In this article, the authors describe the performance model that guides a current Alpha processor design project. The model allows the designers to conduct architectural explorations over a large range of processor organizations. In the process, they arrived at a chip organization that met Digital's design goal of building a better/ faster/cheaper microprocessor.