The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
The Alpha 21264 Microprocessor
IEEE Micro
System Optimization for OLTP Workloads
IEEE Micro
Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
A performance methodology for commercial servers
IBM Journal of Research and Development
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
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We developed a 1.3-GHz SPARC-V9 processor:the SPARC64 V. This processor is designed to address requirements for enterprise servers and high-performance computing. Processing speed under multi-user interactive workloads is very sensitive to system balance because of the large number of memory requests included. From many years of experience with such workloads in mainframe system developments, we give importance to design a well-balanced communication structure. To accomplish this task,a system-level performance study must begin at an early phase. Therefore we developed a performance model, which consists of a detailed processor model and detailed memory model, before hardware design was started. We updated it continuously. Once a logic simulator became available, we used it to verify the performance model for improving its accuracy. The model quite effectively enabled us to achieve performance goals and finish development quickly. This paper describes the SPARC64 V microarchitecture and performance analyses for hardware design.