HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Improved automatic testcase synthesis for performance model validation
Proceedings of the 19th annual international conference on Supercomputing
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During the development of high-performance processors, software performance models are used to get performance estimates. These models are not cycle-accurate, so their results can have significant errors, leading to performance surprises after hardware is built. Some performance tests can run directly on the logic simulators, to get more accurate results, but those simulators cannot run large interactive workloads with I/O and much Operating System code. So the accurate performance estimates from logic simulators are only available for application code, and are not adequate for evaluation of powerful server systems that will primarily run large interactive workloads. We discuss a software tool system, the "Reverse Tracer" that generates executable performance tests from an instruction trace of the workload. The generated performance tests retain the essential performance characteristics of multi-user I/O-intensive workloads without doing any real I/O, so they can run in logic simulation to measure performance accurately before hardware is built.