Instruction cache fetch policies for speculative execution

Authors:
Dennis Lee;Jean-Loup Baer;Brad Calder;Dirk Grunwald
Affiliations:
Department of Computer Science and Engineering, Box 352350, University of Washington, Seattle, WA;Department of Computer Science and Engineering, Box 352350, University of Washington, Seattle, WA;Department of Computer Science, Campus Box 430, University of Colorado, Boulder, CO;Department of Computer Science, Campus Box 430, University of Colorado, Boulder, CO
Venue:
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Year:
1995

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Abstract

Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, a technique whereby the processor continues executing the predicted path of a branch before the branch condition is resolved.In this paper, we investigate the implications of speculative execution on instruction cache performance. We explore policies for managing instruction cache misses ranging from aggressive policies (always fetch on the speculative path) to conservative ones (wait until branches are resolved). We test these policies and their interaction with next-line prefetching by simulating the effects on instruction caches with varying architectural parameters. Our results suggest that an aggressive policy combined with next-line prefetching is best for small latencies while more conservative policies are preferable for large latencies.