Theoretical modeling of superscalar processor performance
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This paper presents a statistical approach to estimating the performance of a superscalar processor. Traditional trace-driven simulators can take a large amount time to conduct a performance evaluation of a machine, especially as the number of instructions increases. The result of this type of simulation is typically tied to the particular trace that was run. Elements such as dependencies, delays, and stalls are all a direct result of the particular trace being run, and can differ from trace to trace. This paper describes a model designed to separate simulation results from a specific trace. Rather than running a trace-driven simulation, a statistical model is employed, more specifically a Poisson distribution, to predict how these types of delay affects performance. Through the use of this statistical model, a performance evaluation can be conducted using a general code model, with specific stall rates, rather than a particular code trace. This model allows simulations to quickly run tens of millions of instructions and evaluate the performance of a particular micro-architecture while at the same time, allowing the flexibility to change the structure of the architecture.