Can Trace-Driven Simulators Accurately Predict Superscalar Performance?

Authors:
Bryan Black;Andrew S. Huang;Mikko H. Lipasti;John Paul Shen
Affiliations:
-;-;-;-
Venue:
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Year:
1996

Citing 0
Cited 6

Calibration of Microprocessor Performance Models

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Evaluating the impact of the simulation environment on experimentation results

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A superscalar simulation employing poisson distributed stalls

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Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach

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On the simulation of large-scale architectures using multiple application abstraction levels

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Accurately modeling superscalar processor performance with reduced trace

Journal of Parallel and Distributed Computing

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Abstract

There are four crucial issues associated with performance simulators: simulator retargetability, simulator validation, simulation speed and simulation accuracy. This paper documents our experiences in developing performance simulators and our recent findings in using these simulators. We are concerned with all four of the crucial issues. Our first-generation tool, VMW, focused on achieving retargetability. Our second-generation tool, MW, significantly improved simulation speed. Recently we validated a PowerPC 604 simulator model, generated using MW, against an actual PowerPC 604 hardware system. We also present results on simulating extremely long traces on our PowerPC 620 model and highlight potential inaccuracies that can result from trace sampling. As processor complexity continues to increase at a rapid rate and microarchitectures continue to become more speculative, it is not clear whether the trace-driven paradigm of performance simulation can continue to effectively predict actual machine performance.