On the simulation of large-scale architectures using multiple application abstraction levels

  • Authors:

  • Alejandro Rico;Felipe Cabarcas;Carlos Villavieja;Milan Pavlovic;Augusto Vega;Yoav Etsion;Alex Ramirez;Mateo Valero

  • Affiliations:

  • Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain;Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain

  • Venue:
  • ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
  • Year:
  • 2012

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Abstract

Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are they meant for this. Moreover, microarchitecture design decisions are irrelevant, or even misleading, for early processor design stages and high-level explorations. This allows one to raise the abstraction level of the simulated architecture, and also the application abstraction level, as it does not necessarily have to be represented as an instruction stream. In this paper we introduce a definition of different application abstraction levels, and how these are employed in TaskSim, a multi-core architecture simulator, to provide several architecture modeling abstractions, and simulate large-scale architectures with hundreds of cores. We compare the simulation speed of these abstraction levels to the ones in existing simulation tools, and also evaluate their utility and accuracy. Our simulations show that a very high-level abstraction, which may be even faster than native execution, is useful for scalability studies on parallel applications; and that just simulating explicit memory transfers, we achieve accurate simulations for architectures using non-coherent scratchpad memories, with just a 25x slowdown compared to native execution. Furthermore, we revisit trace memory simulation techniques, that are more abstract than instruction-by-instruction simulations and provide an 18x simulation speedup.