The SARC Architecture

Authors:
Alex Ramirez;Felipe Cabarcas;Ben Juurlink;Mauricio Alvarez Mesa;Friman Sanchez;Arnaldo Azevedo;Cor Meenderinck;Catalin Ciobanu;Sebastian Isaza;Gerogi Gaydadjiev
Affiliations:
Barcelona Supercomputing Center;Barcelona Supercomputing Center;Technische Universitat Berlin;Universitat Politecnica de Catalunya;Universitat Politecnica de Catalunya;Delft University of Technology;Delft University of Technology;Delft University of Technology;Delft University of Technology;Delft University of Technology
Venue:
IEEE Micro
Year:
2010

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Abstract

The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.