Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Implementation of precise interrupts in pipelined processors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Symbolic Model Checking
Formal Verification of Hardware Design
Formal Verification of Hardware Design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
3.3 Performance Test Case Generation for Microprocessors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Zen and the Art of Alpha Verification
ICCD '98 Proceedings of the International Conference on Computer Design
A visualization-based microarchitecture workbench
A visualization-based microarchitecture workbench
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a methodology for validating microarchitecturespecifications. We view microarchitecture features as specificoperations on entries of various buffers in the processor. Ourvalidation approach is to determine the functionality of a buffertype, model its operations at the microarchitecture level usingabstract finite state machine (FSM) models, and rigorously generateinstruction sequences that systematically exercise the model of eachinstance of that buffer type. A high-level test sequence is derivedbased on the abstract FSM model using FSM testing techniques, andthen translated to a test program that exercises the functionality ofeach buffer entry. This methodology is applied to themicroarchitecture specifications of the PowerPC 604. Theeffectiveness of the sequences generated using our methodology iscompared with that of some real and randomly-generated programs.Simulation results show that all targeted FSM transitions are coveredby our sequences with at least 1000 × and 3 × fewerinstructions than real and randomly-generated programs, respectively.